As known, according to a solution that is currently very widespread in the microelectronics industry, substrates of integrated devices are often formed from wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called "SOI" (Silicon-on-Insulator) wafers have been proposed, having two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer (see for example the article "Silicon-on-Insulator Wafer Bonding Wafer Thinning Technological Evaluations" by J. Hausman, G. A. Spierings, U. K. P. Bierman and J. A. Pals, Japanese Journal of Applied Physics, Vol. 28, No. 8, August 1989, pp. 1426-1443).
Attention has recently been paid to SOI wafers, since integrated circuits that have a substrate formed from wafers of this type have advantages compared with similar circuits formed on conventional substrates, i.e. consisting of monocrystalline silicon alone. These advantages can be summarized as follows:
a) faster switching speed; PA1 b) greater noise immunity; PA1 c) smaller loss currents; PA1 d) elimination of parasitic component switching phenomena ("SCR latch-up"); PA1 e) reduction of parasitic capacitances; PA1 f) greater resistance to radiation effects; and PA1 g) greater packing density of the components.
A typical process for manufacturing SOI wafers is described in the aforementioned article, and is based on physically uniting two monocrystalline silicon wafers ("wafer bonding" process). In particular, according to this process, one of the two wafers is oxidized, and after cleaning operations, is bonded to the other wafer. After thermal annealing, the outer surface of the oxidized wafer is ground and then polished until the required thickness is obtained (for example 1.mu.m). An epitaxial layer for integrating electronic components is subsequently optionally grown on the thinner monocrystalline silicon layer. The wafers obtained through the conventional wafer bonding method have excellent electrical characteristics, but have undeniably high costs (approximately six times greater than the cost of the standard substrates).
Other methodologies, such as ZHR, SIMOX, etc., are described in the article "SOI Technologies: Their Past, Present and Future" by J. Haisha, Journal de Physique, Colloque C4, Supplement a no. 9, Tome 49, September 1988. These latter techniques have also not yet reached an industrial acceptance, and have some limitations. In fact, they do not provide layers of monocrystalline silicon on large oxide areas. They often have high levels of defects owing to the dislocations generated by stresses induced by the buried oxide, or they do not support formation of high voltage components as with SIMOX technology, where the oxide thickness obtained by oxygen implantation is approximately 100-200 nm.